Silicon carbide (SiC) Schottky rectifiers are extremely fast with zero minority carrier (hole) reverse recovery charge (Qrr). The only charge participated during the switching of SiC Schottky Rectifiers is the majority carrier (electron) junction capacitive charge (Qc). The Qc of SiC Schottky Rectifiers does not change with temperatures or operation conditions such as forward current and the reverse bias. On the other hand, the Qrr of silicon PiN diodes usually increases significantly with temperature, forward current and reverse bias, unless some “lifetime killer” defects were introduced to reduce the excess concentration of injected minority carriers, this, however, will diminish the benefit (low forward voltage) of conductivity modulation effect that originally brought by the minority carriers.
Today, most commercial SiC Schottky rectifiers are not plain Schottky barriers diodes (SBD), instead, some additional structures are introduced to form the so called junction barrier controlled Schottky (JBS) or merged PiN Schottky (MPS) rectifiers. These structures are used to suppress the leakage current at reverse bias and enhance the capability of withstanding inrush current. So, how fast and how rugged todays SiC Schottky rectifiers can be? There is a white paper published by Cree (Wolfspeed) demonstrated that their 650V and 1200V SiC JBS can withstand dV/dt with no failures up to 295V/ns and 490V/ns, respectively. A lower dv/dt does not mean the 650V SiC JBS is slower, in fact, in that white paper both 650V and 1200V SiC JBS were switched off in about 1.35 ns, the reported value simply reflect the voltage swing (400V vs. 800V) used in the testing setup and are not the “speed limit” of the devices.
With such high switching speed, the parasitics of packages will affect not only the noise level (EMI/EMC) but also the switching loss and will put a limit on the maximum achievable switching frequency. Common package types can have very different parasitics. For example, a paper published by Prof. Juan Rivas-Davila’s group at Stanford University showed that the surface mount version of through hole packages D2PAK (TO-263) have a 2X to 8X smaller parasitic inductances compared to the large through-hole packages TO-247. In another application note, Infineon showed that the parasitic inductances of packages can be further reduced with surface mount quad flat no lead (QFN) packages where the DC/AC Source inductance of their Thinpak (QFN5x6) is only 1.6nH/1.46nH, much lower than 4.7nH/4.5nH of DPAK (TO-252) and 8.4nH/7.4nH of TO-220FP . The DC/AC Drain inductances of DPAK and QFN5x6 are also significantly reduced from TO-220FP’s 5.8nH/5.2nH to 0.09nH/0.1nH and 0.05nH/0.02nH, respectively. These reports suggest that the surface mount packages, no matter it is leadless (such as QFN5x6) or with lead (such as DPAK), are going to be more suitable for devices with high switching speed including SiC Schottky Rectifiers, SiC MOSFETs and GaN HEMTs. Anyway, picking a right package may be just as important as optimizing the PCB traces in improving the efficiency and electromagnetic compatibility.
